Q. Discuss the role of a bus arbiter in a multiprocessor configuration.

Ans, Bus arbiter: Which functions to resolve priority between bus masters and allows only one device at a time to access the shared bus. The 8289 bus arbiter controls the interface of a bus master to a shared bus. This is designed to function with the 8086/8088 microprocessors. Each bus master or microprocessor requires an arbiter for the interface to the shared bus, which Intel calls the MULTIBUS and IBM calls the MICRO CHANNEL.

The shared bus used only to pass information from one microprocessor to another; otherwise, the bus master function in their own local bus modes by using their own local programs, memory, and I/O space. Microprocessors connected in this kind of system are often called parallel or distributed processors because they can execute software and perform tasks in parallel.

Q. What is a co-processor? What is its use in a typical microprocessor based system.

Ans 8087 NDP (numerical data processor) is also known as math co-processor which is used in parallel with the main processor for number crunching applications, which would otherwise require complex programming. It is also faster than 8086/8088 processor in performing mathematical computation. It has its own specialized instruction sets to handle mathematical programs.

It is a processor which works in parallel with the main processor. It has its own set of specialized instructions. The number crunching part of the program is executed by 8087. Instruction for 8087 are written in the main program interspersed with the 8086 instructions. All the 8087 instruction codes have 11011 as the most significant bits of their first code byte.

Q. What is a PCI bus? Discuss its features and usage.

Ans Peripheral Component Interconnect (PCI): This bus was developed by Intel and introduced in 1993. It is geared specifically to fifth- and sixth-generation systems, although the latest generation 486 motherboards use PCI as well. PCI bus has plug – and – play characteristics and the ability to function with a 64-bit data bus. A PCI interface contains series of registers, located in a small memory device on the PCI interface that contains information about the board.

Q. What is segmentation? What are its advantages? How is segmentation implemented in typical microprocessors?

Ans Segment memory addressing divides the memory into many segments. Each of these segments can be considered as a linear memory space. Each of these segment is addressed by a segment register.

However since the segment register is 16 bit wide and the memory needs 20 bits for an address the 8086 appends four bits segment register to obtain the segment address. Therefore, to address the segment 10000H by , say the SS register, the SS must contain 1000H.

The first advantage that memory segmentation has is that only 16 bit registers are required both to store segment base address as well as offset address. This makes the internal circuitry easier to built as it removes the requirement for 20 bits register in case the linear addressing method is used. The second advantage is relocatability.

Q. Differentiate between synchronous and asynchronous types of serial communication.

Ans Serial data communication uses two basic types, synchronous and asynchronous. With synchronous communications, the two devices initially synchronize themselves to each other, and then continually send characters to stay in sync. Even when data is not really being sent, a constant flow of bits allows each device to know where the other is at any given time. That is, each character that is sent is either actual data or an idle character.

Asynchronous means "no synchronization", and thus does not require sending and receiving idle characters. However, the beginning and end of each byte of data must be identified by start and stop bits. The start bit indicates when the data byte is about to begin and the stop bit signals when it ends. The requirement to send these additional two bits causes asynchronous communication to be slightly slower than synchronous however it has the advantage that the processor does not have to deal with the additional idle characters.

Q. What is DRAM? What do you understand by DRAM refreshing? Show how DRAM can be interfaced to a microprocessor.

Ans Dynamic RAM (DRAM) is essentially the same as SRAM, except that it retains data for only 2 or 4 ms on an internal capacitor. After 2 or 4 ms, the contents of the DRAM must be completely rewritten (refreshed) because the capacitors, which store logic 1 or logic 0, lose their charges. The entire content of the memory is refreshed with 256 reads in a 2-to-4 ms interval. Refreshing also occurs during a write, a read or during a special refresh cycle.

Q.53 Explain the functions of the following:
(i) Debugger (ii) Assembler (iii) Linker

Ans (i) Debugger: It is a program which allows user to test and debug programs. All computers including microprocessor kits provide debugging facility. To detect errors a program can be tested in single steps. Each step of the program is executed and tested. The debugger allows the user to examine the contents of registers and memory locations after each step of execution. This also provides facility to insert breakpoint in the programs.
(ii) Assembler: An assembler or macro-assembler generally forms a part of the operating system. Which translates a assembly language program into machine language program.
(iii) Linker: A large program is divided in smaller programs known as modules. A linker is a program which links smaller programs together to form a large program. While developing a program subroutines, which are stored in library file, are frequently used in the program. The linker also links these subroutines with the main program.